/*
 * Copyright (c) 2014, Freescale Semiconductor, Inc.
 * All rights reserved.
 *
 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 */
/*
 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
 *
 * This file was generated automatically and any changes may be lost.
 */
#ifndef __HW_MTB_REGISTERS_H__
#define __HW_MTB_REGISTERS_H__

#include "regs.h"

/*
 * MKL05Z4 MTB
 *
 * Micro Trace Buffer
 *
 * Registers defined in this header file:
 * - HW_MTB_POSITION - MTB Position Register
 * - HW_MTB_MASTER - MTB Master Register
 * - HW_MTB_FLOW - MTB Flow Register
 * - HW_MTB_BASE - MTB Base Register
 * - HW_MTB_MODECTRL - Integration Mode Control Register
 * - HW_MTB_TAGSET - Claim TAG Set Register
 * - HW_MTB_TAGCLEAR - Claim TAG Clear Register
 * - HW_MTB_LOCKACCESS - Lock Access Register
 * - HW_MTB_LOCKSTAT - Lock Status Register
 * - HW_MTB_AUTHSTAT - Authentication Status Register
 * - HW_MTB_DEVICEARCH - Device Architecture Register
 * - HW_MTB_DEVICECFG - Device Configuration Register
 * - HW_MTB_DEVICETYPID - Device Type Identifier Register
 * - HW_MTB_PERIPHIDn - Peripheral ID Register
 * - HW_MTB_PERIPHIDn - Peripheral ID Register
 * - HW_MTB_PERIPHIDn - Peripheral ID Register
 * - HW_MTB_PERIPHIDn - Peripheral ID Register
 * - HW_MTB_PERIPHIDn - Peripheral ID Register
 * - HW_MTB_PERIPHIDn - Peripheral ID Register
 * - HW_MTB_PERIPHIDn - Peripheral ID Register
 * - HW_MTB_PERIPHIDn - Peripheral ID Register
 * - HW_MTB_COMPIDn - Component ID Register
 *
 * - hw_mtb_t - Struct containing all module registers.
 */

//! @name Module base addresses
//@{
#ifndef REGS_MTB_BASE
#define HW_MTB_INSTANCE_COUNT (1U) //!< Number of instances of the MTB module.
#define REGS_MTB_BASE (0xF0000000U) //!< Base address for MTB.
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_MTB_POSITION - MTB Position Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_POSITION - MTB Position Register (RW)
 *
 * Reset value: 0x00000000U
 *
 * The MTB_POSITION register is the trace write address pointer and wrap bit.
 * This register can be modified by the explicit programming model writes. It is
 * also automatically updated by the MTB hardware when trace packets are being
 * recorded.
 */
typedef union _hw_mtb_position
{
    uint32_t U;
    struct _hw_mtb_position_bitfields
    {
        uint32_t RESERVED0 : 2;        //!< [1:0]
        uint32_t WRAP : 1;             //!< [2]
        uint32_t POINTER : 29;         //!< [31:3] Trace Packet Address Pointer
    } B;
} hw_mtb_position_t;
#endif

/*!
 * @name Constants and macros for entire MTB_POSITION register
 */
//@{
#define HW_MTB_POSITION_ADDR     (REGS_MTB_BASE + 0x0U)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_POSITION          (*(__IO hw_mtb_position_t *) HW_MTB_POSITION_ADDR)
#define HW_MTB_POSITION_RD()     (HW_MTB_POSITION.U)
#define HW_MTB_POSITION_WR(v)    (HW_MTB_POSITION.U = (v))
#define HW_MTB_POSITION_SET(v)   (BME_OR32(HW_MTB_POSITION_ADDR, (uint32_t)(v)))
#define HW_MTB_POSITION_CLR(v)   (BME_AND32(HW_MTB_POSITION_ADDR, (uint32_t)(~(v))))
#define HW_MTB_POSITION_TOG(v)   (BME_XOR32(HW_MTB_POSITION_ADDR, (uint32_t)(v)))
#endif
//@}

/*
 * Constants & macros for individual MTB_POSITION bitfields
 */

/*!
 * @name Register MTB_POSITION, field WRAP[2] (RW)
 *
 * This bit is set to 1 automatically when the POINTER value wraps as determined
 * by the MTB_MASTER[MASK] bit in the MASTER Trace Control Register. A debug
 * agent can use the WRAP bit to determine whether the trace information above and
 * below the pointer address is valid.
 */
//@{
#define BP_MTB_POSITION_WRAP (2U)          //!< Bit position for MTB_POSITION_WRAP.
#define BM_MTB_POSITION_WRAP (0x00000004U) //!< Bit mask for MTB_POSITION_WRAP.
#define BS_MTB_POSITION_WRAP (1U)          //!< Bit field size in bits for MTB_POSITION_WRAP.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_POSITION_WRAP field.
#define BR_MTB_POSITION_WRAP (BME_UBFX32(HW_MTB_POSITION_ADDR, BP_MTB_POSITION_WRAP, BS_MTB_POSITION_WRAP))
#endif

//! @brief Format value for bitfield MTB_POSITION_WRAP.
#define BF_MTB_POSITION_WRAP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MTB_POSITION_WRAP), uint32_t) & BM_MTB_POSITION_WRAP)

#ifndef __LANGUAGE_ASM__
//! @brief Set the WRAP field to a new value.
#define BW_MTB_POSITION_WRAP(v) (BME_BFI32(HW_MTB_POSITION_ADDR, ((uint32_t)(v) << BP_MTB_POSITION_WRAP), BP_MTB_POSITION_WRAP, 1))
#endif
//@}

/*!
 * @name Register MTB_POSITION, field POINTER[31:3] (RW)
 *
 * Trace packet address pointer. Because a packet consists of two words, the
 * POINTER field is the address of the first word of a packet. This field contains
 * bits[31:3] of the RAM address that points to the next unused memory location
 * for the trace data. This is an empty ascending location and is automatically
 * updated. A debug agent can add the value of POINTER to the value of MTB_BASE to
 * obtain the absolute pointer address as seen on the system AHB bus interface.
 * The size of the RAM is parameterized and the most significant bits of the
 * POINTER field are RAZ/WI. POSITION register bits greater than or equal to 15 are
 * RAZ/WI, therefore, the active POINTER field bits are [11:0].
 */
//@{
#define BP_MTB_POSITION_POINTER (3U)       //!< Bit position for MTB_POSITION_POINTER.
#define BM_MTB_POSITION_POINTER (0xFFFFFFF8U) //!< Bit mask for MTB_POSITION_POINTER.
#define BS_MTB_POSITION_POINTER (29U)      //!< Bit field size in bits for MTB_POSITION_POINTER.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_POSITION_POINTER field.
#define BR_MTB_POSITION_POINTER (BME_UBFX32(HW_MTB_POSITION_ADDR, BP_MTB_POSITION_POINTER, BS_MTB_POSITION_POINTER))
#endif

//! @brief Format value for bitfield MTB_POSITION_POINTER.
#define BF_MTB_POSITION_POINTER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MTB_POSITION_POINTER), uint32_t) & BM_MTB_POSITION_POINTER)

#ifndef __LANGUAGE_ASM__
//! @brief Set the POINTER field to a new value.
#define BW_MTB_POSITION_POINTER(v) (BME_BFI32(HW_MTB_POSITION_ADDR, ((uint32_t)(v) << BP_MTB_POSITION_POINTER), BP_MTB_POSITION_POINTER, 29))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_MTB_MASTER - MTB Master Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_MASTER - MTB Master Register (RW)
 *
 * Reset value: 0x00000080U
 *
 * The MTB_MASTER register contains the main program trace enable plus other
 * trace controls. This register can be modified by the explicit programming model
 * writes. MTB_MASTER[EN] and MTB_MASTER[HALTREQ] fields are also automatically
 * updated by the MTB hardware. Before the MTB_MASTER[EN] or MTB_MASTER[TSTARTEN]
 * bits are set to 1, software must initialize the MTB_POSITION and MTB_FLOW
 * registers. If the MTB_FLOW[WATERMARK] field is used to stop tracing or to halt the
 * processor, the MTB_MASTER[MASK] field must still be set to a value that
 * prevents the MTB_POSITION[POINTER] field from wrapping before it reaches the
 * MTB_FLOW[WATERMARK] value. The format of this mask field is different than the
 * MTBDWT_MASKn[MASK].
 */
typedef union _hw_mtb_master
{
    uint32_t U;
    struct _hw_mtb_master_bitfields
    {
        uint32_t MASK : 5;             //!< [4:0] Mask
        uint32_t TSTARTEN : 1;         //!< [5] Trace start input enable
        uint32_t TSTOPEN : 1;          //!< [6] Trace stop input enable
        uint32_t SFRWPRIV : 1;         //!< [7] Special Function Register Write
                                       //! Privilege bit
        uint32_t RAMPRIV : 1;          //!< [8] RAM privilege bit
        uint32_t HALTREQ : 1;          //!< [9] Halt request bit
        uint32_t RESERVED0 : 21;       //!< [30:10]
        uint32_t EN : 1;               //!< [31] Main trace enable bit
    } B;
} hw_mtb_master_t;
#endif

/*!
 * @name Constants and macros for entire MTB_MASTER register
 */
//@{
#define HW_MTB_MASTER_ADDR       (REGS_MTB_BASE + 0x4U)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_MASTER            (*(__IO hw_mtb_master_t *) HW_MTB_MASTER_ADDR)
#define HW_MTB_MASTER_RD()       (HW_MTB_MASTER.U)
#define HW_MTB_MASTER_WR(v)      (HW_MTB_MASTER.U = (v))
#define HW_MTB_MASTER_SET(v)     (BME_OR32(HW_MTB_MASTER_ADDR, (uint32_t)(v)))
#define HW_MTB_MASTER_CLR(v)     (BME_AND32(HW_MTB_MASTER_ADDR, (uint32_t)(~(v))))
#define HW_MTB_MASTER_TOG(v)     (BME_XOR32(HW_MTB_MASTER_ADDR, (uint32_t)(v)))
#endif
//@}

/*
 * Constants & macros for individual MTB_MASTER bitfields
 */

/*!
 * @name Register MTB_MASTER, field MASK[4:0] (RW)
 *
 * This value determines the maximum size of the trace buffer in RAM. It
 * specifies the most-significant bit of the MTB_POSITION[POINTER] field that can be
 * updated by automatic increment. If the trace tries to advance past this power of
 * two, the MTB_POSITION[WRAP] bit is set to 1, the MTB_POSITION[POINTER[MASK:0]]
 * bits are set to zero, and the MTB_POSITION[POINTER[11:MASK+1]] bits remain
 * unchanged. This field causes the trace packet information to be stored in a
 * circular buffer of size 2^[MASK+4] bytes, that can be positioned in memory at
 * multiples of this size. Valid values of this field are zero to 11. Values greater
 * than the maximum have the same effect as the maximum.
 */
//@{
#define BP_MTB_MASTER_MASK   (0U)          //!< Bit position for MTB_MASTER_MASK.
#define BM_MTB_MASTER_MASK   (0x0000001FU) //!< Bit mask for MTB_MASTER_MASK.
#define BS_MTB_MASTER_MASK   (5U)          //!< Bit field size in bits for MTB_MASTER_MASK.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_MASTER_MASK field.
#define BR_MTB_MASTER_MASK   (BME_UBFX32(HW_MTB_MASTER_ADDR, BP_MTB_MASTER_MASK, BS_MTB_MASTER_MASK))
#endif

//! @brief Format value for bitfield MTB_MASTER_MASK.
#define BF_MTB_MASTER_MASK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MTB_MASTER_MASK), uint32_t) & BM_MTB_MASTER_MASK)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MASK field to a new value.
#define BW_MTB_MASTER_MASK(v) (BME_BFI32(HW_MTB_MASTER_ADDR, ((uint32_t)(v) << BP_MTB_MASTER_MASK), BP_MTB_MASTER_MASK, 5))
#endif
//@}

/*!
 * @name Register MTB_MASTER, field TSTARTEN[5] (RW)
 *
 * If this bit is 1 and the TSTART signal is HIGH, then the EN bit is set to 1.
 * Tracing continues until a stop condition occurs.
 */
//@{
#define BP_MTB_MASTER_TSTARTEN (5U)        //!< Bit position for MTB_MASTER_TSTARTEN.
#define BM_MTB_MASTER_TSTARTEN (0x00000020U) //!< Bit mask for MTB_MASTER_TSTARTEN.
#define BS_MTB_MASTER_TSTARTEN (1U)        //!< Bit field size in bits for MTB_MASTER_TSTARTEN.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_MASTER_TSTARTEN field.
#define BR_MTB_MASTER_TSTARTEN (BME_UBFX32(HW_MTB_MASTER_ADDR, BP_MTB_MASTER_TSTARTEN, BS_MTB_MASTER_TSTARTEN))
#endif

//! @brief Format value for bitfield MTB_MASTER_TSTARTEN.
#define BF_MTB_MASTER_TSTARTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MTB_MASTER_TSTARTEN), uint32_t) & BM_MTB_MASTER_TSTARTEN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TSTARTEN field to a new value.
#define BW_MTB_MASTER_TSTARTEN(v) (BME_BFI32(HW_MTB_MASTER_ADDR, ((uint32_t)(v) << BP_MTB_MASTER_TSTARTEN), BP_MTB_MASTER_TSTARTEN, 1))
#endif
//@}

/*!
 * @name Register MTB_MASTER, field TSTOPEN[6] (RW)
 *
 * If this bit is 1 and the TSTOP signal is HIGH, then the EN bit is set to 0.
 * If a trace packet is being written to memory, the write is completed before
 * tracing is stopped.
 */
//@{
#define BP_MTB_MASTER_TSTOPEN (6U)         //!< Bit position for MTB_MASTER_TSTOPEN.
#define BM_MTB_MASTER_TSTOPEN (0x00000040U) //!< Bit mask for MTB_MASTER_TSTOPEN.
#define BS_MTB_MASTER_TSTOPEN (1U)         //!< Bit field size in bits for MTB_MASTER_TSTOPEN.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_MASTER_TSTOPEN field.
#define BR_MTB_MASTER_TSTOPEN (BME_UBFX32(HW_MTB_MASTER_ADDR, BP_MTB_MASTER_TSTOPEN, BS_MTB_MASTER_TSTOPEN))
#endif

//! @brief Format value for bitfield MTB_MASTER_TSTOPEN.
#define BF_MTB_MASTER_TSTOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MTB_MASTER_TSTOPEN), uint32_t) & BM_MTB_MASTER_TSTOPEN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TSTOPEN field to a new value.
#define BW_MTB_MASTER_TSTOPEN(v) (BME_BFI32(HW_MTB_MASTER_ADDR, ((uint32_t)(v) << BP_MTB_MASTER_TSTOPEN), BP_MTB_MASTER_TSTOPEN, 1))
#endif
//@}

/*!
 * @name Register MTB_MASTER, field SFRWPRIV[7] (RW)
 *
 * If this bit is 0, then user or privileged AHB read and write accesses to the
 * MTB_RAM Special Function Registers (programming model) are permitted. If this
 * bit is 1, then only privileged write accesses are permitted; user write
 * accesses are ignored. The HPROT[1] signal determines if an access is user or
 * privileged. Note MTB_RAM SFR read access are not controlled by this bit and are
 * always permitted.
 */
//@{
#define BP_MTB_MASTER_SFRWPRIV (7U)        //!< Bit position for MTB_MASTER_SFRWPRIV.
#define BM_MTB_MASTER_SFRWPRIV (0x00000080U) //!< Bit mask for MTB_MASTER_SFRWPRIV.
#define BS_MTB_MASTER_SFRWPRIV (1U)        //!< Bit field size in bits for MTB_MASTER_SFRWPRIV.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_MASTER_SFRWPRIV field.
#define BR_MTB_MASTER_SFRWPRIV (BME_UBFX32(HW_MTB_MASTER_ADDR, BP_MTB_MASTER_SFRWPRIV, BS_MTB_MASTER_SFRWPRIV))
#endif

//! @brief Format value for bitfield MTB_MASTER_SFRWPRIV.
#define BF_MTB_MASTER_SFRWPRIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MTB_MASTER_SFRWPRIV), uint32_t) & BM_MTB_MASTER_SFRWPRIV)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SFRWPRIV field to a new value.
#define BW_MTB_MASTER_SFRWPRIV(v) (BME_BFI32(HW_MTB_MASTER_ADDR, ((uint32_t)(v) << BP_MTB_MASTER_SFRWPRIV), BP_MTB_MASTER_SFRWPRIV, 1))
#endif
//@}

/*!
 * @name Register MTB_MASTER, field RAMPRIV[8] (RW)
 *
 * If this bit is 0, then user or privileged AHB read and write accesses to the
 * RAM are permitted. If this bit is 1, then only privileged AHB read and write
 * accesses to the RAM are permitted and user accesses are RAZ/WI. The HPROT[1]
 * signal determines if an access is a user or privileged mode reference.
 */
//@{
#define BP_MTB_MASTER_RAMPRIV (8U)         //!< Bit position for MTB_MASTER_RAMPRIV.
#define BM_MTB_MASTER_RAMPRIV (0x00000100U) //!< Bit mask for MTB_MASTER_RAMPRIV.
#define BS_MTB_MASTER_RAMPRIV (1U)         //!< Bit field size in bits for MTB_MASTER_RAMPRIV.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_MASTER_RAMPRIV field.
#define BR_MTB_MASTER_RAMPRIV (BME_UBFX32(HW_MTB_MASTER_ADDR, BP_MTB_MASTER_RAMPRIV, BS_MTB_MASTER_RAMPRIV))
#endif

//! @brief Format value for bitfield MTB_MASTER_RAMPRIV.
#define BF_MTB_MASTER_RAMPRIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MTB_MASTER_RAMPRIV), uint32_t) & BM_MTB_MASTER_RAMPRIV)

#ifndef __LANGUAGE_ASM__
//! @brief Set the RAMPRIV field to a new value.
#define BW_MTB_MASTER_RAMPRIV(v) (BME_BFI32(HW_MTB_MASTER_ADDR, ((uint32_t)(v) << BP_MTB_MASTER_RAMPRIV), BP_MTB_MASTER_RAMPRIV, 1))
#endif
//@}

/*!
 * @name Register MTB_MASTER, field HALTREQ[9] (RW)
 *
 * This bit is connected to the halt request signal of the trace logic, EDBGRQ.
 * When HALTREQ is set to 1, the EDBFGRQ is asserted if DBGEN (invasive debug
 * enable, one of the debug authentication interface signals) is also HIGH. The
 * HALTREQ bit can be automatically set to 1 using the MTB_FLOW[WATERMARK] field.
 */
//@{
#define BP_MTB_MASTER_HALTREQ (9U)         //!< Bit position for MTB_MASTER_HALTREQ.
#define BM_MTB_MASTER_HALTREQ (0x00000200U) //!< Bit mask for MTB_MASTER_HALTREQ.
#define BS_MTB_MASTER_HALTREQ (1U)         //!< Bit field size in bits for MTB_MASTER_HALTREQ.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_MASTER_HALTREQ field.
#define BR_MTB_MASTER_HALTREQ (BME_UBFX32(HW_MTB_MASTER_ADDR, BP_MTB_MASTER_HALTREQ, BS_MTB_MASTER_HALTREQ))
#endif

//! @brief Format value for bitfield MTB_MASTER_HALTREQ.
#define BF_MTB_MASTER_HALTREQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MTB_MASTER_HALTREQ), uint32_t) & BM_MTB_MASTER_HALTREQ)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HALTREQ field to a new value.
#define BW_MTB_MASTER_HALTREQ(v) (BME_BFI32(HW_MTB_MASTER_ADDR, ((uint32_t)(v) << BP_MTB_MASTER_HALTREQ), BP_MTB_MASTER_HALTREQ, 1))
#endif
//@}

/*!
 * @name Register MTB_MASTER, field EN[31] (RW)
 *
 * When this bit is 1, trace data is written into the RAM memory location
 * addressed by MTB_POSITION[POINTER]. The MTB_POSITION[POINTER] value auto increments
 * after the trace data packet is written. The EN bit can be automatically set to
 * 0 using the MTB_FLOW[WATERMARK] field and the MTB_FLOW[AUTOSTOP] bit. The EN
 * bit is automatically set to 1 if the TSTARTEN bit is 1 and the TSTART signal
 * is HIGH. The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the TSTOP
 * signal is HIGH. If the EN bit is set to 0 because the MTB_FLOW[WATERMARK]
 * field is set, then it is not automatically set to 1 if the TSTARTEN bit is 1 and
 * the TSTART input is HIGH. In this case, tracing can only be restarted if the
 * MTB_FLOW[WATERMARK] or MTB_POSITION[POINTER] value is changed by software.
 */
//@{
#define BP_MTB_MASTER_EN     (31U)         //!< Bit position for MTB_MASTER_EN.
#define BM_MTB_MASTER_EN     (0x80000000U) //!< Bit mask for MTB_MASTER_EN.
#define BS_MTB_MASTER_EN     (1U)          //!< Bit field size in bits for MTB_MASTER_EN.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_MASTER_EN field.
#define BR_MTB_MASTER_EN     (BME_UBFX32(HW_MTB_MASTER_ADDR, BP_MTB_MASTER_EN, BS_MTB_MASTER_EN))
#endif

//! @brief Format value for bitfield MTB_MASTER_EN.
#define BF_MTB_MASTER_EN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MTB_MASTER_EN), uint32_t) & BM_MTB_MASTER_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the EN field to a new value.
#define BW_MTB_MASTER_EN(v)  (BME_BFI32(HW_MTB_MASTER_ADDR, ((uint32_t)(v) << BP_MTB_MASTER_EN), BP_MTB_MASTER_EN, 1))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_MTB_FLOW - MTB Flow Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_FLOW - MTB Flow Register (RW)
 *
 * Reset value: 0x00000000U
 *
 * The MTB_FLOW register contains the watermark address and the
 * autostop/autohalt control bits.
 */
typedef union _hw_mtb_flow
{
    uint32_t U;
    struct _hw_mtb_flow_bitfields
    {
        uint32_t AUTOSTOP : 1;         //!< [0]
        uint32_t AUTOHALT : 1;         //!< [1]
        uint32_t RESERVED0 : 1;        //!< [2]
        uint32_t WATERMARK : 29;       //!< [31:3] WATERMARK value
    } B;
} hw_mtb_flow_t;
#endif

/*!
 * @name Constants and macros for entire MTB_FLOW register
 */
//@{
#define HW_MTB_FLOW_ADDR         (REGS_MTB_BASE + 0x8U)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_FLOW              (*(__IO hw_mtb_flow_t *) HW_MTB_FLOW_ADDR)
#define HW_MTB_FLOW_RD()         (HW_MTB_FLOW.U)
#define HW_MTB_FLOW_WR(v)        (HW_MTB_FLOW.U = (v))
#define HW_MTB_FLOW_SET(v)       (BME_OR32(HW_MTB_FLOW_ADDR, (uint32_t)(v)))
#define HW_MTB_FLOW_CLR(v)       (BME_AND32(HW_MTB_FLOW_ADDR, (uint32_t)(~(v))))
#define HW_MTB_FLOW_TOG(v)       (BME_XOR32(HW_MTB_FLOW_ADDR, (uint32_t)(v)))
#endif
//@}

/*
 * Constants & macros for individual MTB_FLOW bitfields
 */

/*!
 * @name Register MTB_FLOW, field AUTOSTOP[0] (RW)
 *
 * If this bit is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then the
 * MTB_MASTER[EN] bit is automatically set to 0. This stops tracing.
 */
//@{
#define BP_MTB_FLOW_AUTOSTOP (0U)          //!< Bit position for MTB_FLOW_AUTOSTOP.
#define BM_MTB_FLOW_AUTOSTOP (0x00000001U) //!< Bit mask for MTB_FLOW_AUTOSTOP.
#define BS_MTB_FLOW_AUTOSTOP (1U)          //!< Bit field size in bits for MTB_FLOW_AUTOSTOP.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_FLOW_AUTOSTOP field.
#define BR_MTB_FLOW_AUTOSTOP (BME_UBFX32(HW_MTB_FLOW_ADDR, BP_MTB_FLOW_AUTOSTOP, BS_MTB_FLOW_AUTOSTOP))
#endif

//! @brief Format value for bitfield MTB_FLOW_AUTOSTOP.
#define BF_MTB_FLOW_AUTOSTOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MTB_FLOW_AUTOSTOP), uint32_t) & BM_MTB_FLOW_AUTOSTOP)

#ifndef __LANGUAGE_ASM__
//! @brief Set the AUTOSTOP field to a new value.
#define BW_MTB_FLOW_AUTOSTOP(v) (BME_BFI32(HW_MTB_FLOW_ADDR, ((uint32_t)(v) << BP_MTB_FLOW_AUTOSTOP), BP_MTB_FLOW_AUTOSTOP, 1))
#endif
//@}

/*!
 * @name Register MTB_FLOW, field AUTOHALT[1] (RW)
 *
 * If this bit is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then the
 * MTB_MASTER[HALTREQ] bit is automatically set to 1. If the DBGEN signal is HIGH,
 * the MTB asserts this halt request to the Cortex-M0+ processor by asserting the
 * EDBGRQ signal.
 */
//@{
#define BP_MTB_FLOW_AUTOHALT (1U)          //!< Bit position for MTB_FLOW_AUTOHALT.
#define BM_MTB_FLOW_AUTOHALT (0x00000002U) //!< Bit mask for MTB_FLOW_AUTOHALT.
#define BS_MTB_FLOW_AUTOHALT (1U)          //!< Bit field size in bits for MTB_FLOW_AUTOHALT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_FLOW_AUTOHALT field.
#define BR_MTB_FLOW_AUTOHALT (BME_UBFX32(HW_MTB_FLOW_ADDR, BP_MTB_FLOW_AUTOHALT, BS_MTB_FLOW_AUTOHALT))
#endif

//! @brief Format value for bitfield MTB_FLOW_AUTOHALT.
#define BF_MTB_FLOW_AUTOHALT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MTB_FLOW_AUTOHALT), uint32_t) & BM_MTB_FLOW_AUTOHALT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the AUTOHALT field to a new value.
#define BW_MTB_FLOW_AUTOHALT(v) (BME_BFI32(HW_MTB_FLOW_ADDR, ((uint32_t)(v) << BP_MTB_FLOW_AUTOHALT), BP_MTB_FLOW_AUTOHALT, 1))
#endif
//@}

/*!
 * @name Register MTB_FLOW, field WATERMARK[31:3] (RW)
 *
 * This field contains an address in the same format as the
 * MTB_POSITION[POINTER] field. When the MTB_POSITION[POINTER] matches the WATERMARK field value,
 * actions defined by the AUTOHALT and AUTOSTOP bits are performed.
 */
//@{
#define BP_MTB_FLOW_WATERMARK (3U)         //!< Bit position for MTB_FLOW_WATERMARK.
#define BM_MTB_FLOW_WATERMARK (0xFFFFFFF8U) //!< Bit mask for MTB_FLOW_WATERMARK.
#define BS_MTB_FLOW_WATERMARK (29U)        //!< Bit field size in bits for MTB_FLOW_WATERMARK.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_FLOW_WATERMARK field.
#define BR_MTB_FLOW_WATERMARK (BME_UBFX32(HW_MTB_FLOW_ADDR, BP_MTB_FLOW_WATERMARK, BS_MTB_FLOW_WATERMARK))
#endif

//! @brief Format value for bitfield MTB_FLOW_WATERMARK.
#define BF_MTB_FLOW_WATERMARK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MTB_FLOW_WATERMARK), uint32_t) & BM_MTB_FLOW_WATERMARK)

#ifndef __LANGUAGE_ASM__
//! @brief Set the WATERMARK field to a new value.
#define BW_MTB_FLOW_WATERMARK(v) (BME_BFI32(HW_MTB_FLOW_ADDR, ((uint32_t)(v) << BP_MTB_FLOW_WATERMARK), BP_MTB_FLOW_WATERMARK, 29))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_MTB_BASE - MTB Base Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_BASE - MTB Base Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * The read-only MTB_BASE Register indicates where the RAM is located in the
 * processor memory map. This register is provided to enable auto discovery of the
 * MTB RAM location, by a debug agent and is defined by a hardware design
 * parameter. For these devices, the base address is defined by the expression:
 * MTB_BASE[BASEADDR] = 0x2000_0000 - (RAM_Size/4)
 */
typedef union _hw_mtb_base
{
    uint32_t U;
    struct _hw_mtb_base_bitfields
    {
        uint32_t BASEADDR : 32;        //!< [31:0]
    } B;
} hw_mtb_base_t;
#endif

/*!
 * @name Constants and macros for entire MTB_BASE register
 */
//@{
#define HW_MTB_BASE_ADDR         (REGS_MTB_BASE + 0xCU)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_BASE              (*(__I hw_mtb_base_t *) HW_MTB_BASE_ADDR)
#define HW_MTB_BASE_RD()         (HW_MTB_BASE.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_BASE bitfields
 */

/*!
 * @name Register MTB_BASE, field BASEADDR[31:0] (RO)
 *
 * This value is defined with a hardwired signal and the expression: 0x2000_0000
 * - (RAM_Size/4). For example, if the total RAM capacity is 16 KB, this field
 * is 0x1FFF_F000.
 */
//@{
#define BP_MTB_BASE_BASEADDR (0U)          //!< Bit position for MTB_BASE_BASEADDR.
#define BM_MTB_BASE_BASEADDR (0xFFFFFFFFU) //!< Bit mask for MTB_BASE_BASEADDR.
#define BS_MTB_BASE_BASEADDR (32U)         //!< Bit field size in bits for MTB_BASE_BASEADDR.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_BASE_BASEADDR field.
#define BR_MTB_BASE_BASEADDR (BME_UBFX32(HW_MTB_BASE_ADDR, BP_MTB_BASE_BASEADDR, BS_MTB_BASE_BASEADDR))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_MTB_MODECTRL - Integration Mode Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_MODECTRL - Integration Mode Control Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * This register enables the device to switch from a functional mode, or default
 * behavior, into integration mode. It is hardwired to specific values used
 * during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtb_modectrl
{
    uint32_t U;
    struct _hw_mtb_modectrl_bitfields
    {
        uint32_t MODECTRL : 32;        //!< [31:0]
    } B;
} hw_mtb_modectrl_t;
#endif

/*!
 * @name Constants and macros for entire MTB_MODECTRL register
 */
//@{
#define HW_MTB_MODECTRL_ADDR     (REGS_MTB_BASE + 0xF00U)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_MODECTRL          (*(__I hw_mtb_modectrl_t *) HW_MTB_MODECTRL_ADDR)
#define HW_MTB_MODECTRL_RD()     (HW_MTB_MODECTRL.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_MODECTRL bitfields
 */

/*!
 * @name Register MTB_MODECTRL, field MODECTRL[31:0] (RO)
 *
 * Hardwired to 0x0000_0000
 */
//@{
#define BP_MTB_MODECTRL_MODECTRL (0U)      //!< Bit position for MTB_MODECTRL_MODECTRL.
#define BM_MTB_MODECTRL_MODECTRL (0xFFFFFFFFU) //!< Bit mask for MTB_MODECTRL_MODECTRL.
#define BS_MTB_MODECTRL_MODECTRL (32U)     //!< Bit field size in bits for MTB_MODECTRL_MODECTRL.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_MODECTRL_MODECTRL field.
#define BR_MTB_MODECTRL_MODECTRL (BME_UBFX32(HW_MTB_MODECTRL_ADDR, BP_MTB_MODECTRL_MODECTRL, BS_MTB_MODECTRL_MODECTRL))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_MTB_TAGSET - Claim TAG Set Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_TAGSET - Claim TAG Set Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * The Claim Tag Set Register returns the number of bits that can be set on a
 * read, and enables individual bits to be set on a write. It is hardwired to
 * specific values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtb_tagset
{
    uint32_t U;
    struct _hw_mtb_tagset_bitfields
    {
        uint32_t TAGSET : 32;          //!< [31:0]
    } B;
} hw_mtb_tagset_t;
#endif

/*!
 * @name Constants and macros for entire MTB_TAGSET register
 */
//@{
#define HW_MTB_TAGSET_ADDR       (REGS_MTB_BASE + 0xFA0U)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_TAGSET            (*(__I hw_mtb_tagset_t *) HW_MTB_TAGSET_ADDR)
#define HW_MTB_TAGSET_RD()       (HW_MTB_TAGSET.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_TAGSET bitfields
 */

/*!
 * @name Register MTB_TAGSET, field TAGSET[31:0] (RO)
 *
 * Hardwired to 0x0000_0000
 */
//@{
#define BP_MTB_TAGSET_TAGSET (0U)          //!< Bit position for MTB_TAGSET_TAGSET.
#define BM_MTB_TAGSET_TAGSET (0xFFFFFFFFU) //!< Bit mask for MTB_TAGSET_TAGSET.
#define BS_MTB_TAGSET_TAGSET (32U)         //!< Bit field size in bits for MTB_TAGSET_TAGSET.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_TAGSET_TAGSET field.
#define BR_MTB_TAGSET_TAGSET (BME_UBFX32(HW_MTB_TAGSET_ADDR, BP_MTB_TAGSET_TAGSET, BS_MTB_TAGSET_TAGSET))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_MTB_TAGCLEAR - Claim TAG Clear Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_TAGCLEAR - Claim TAG Clear Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * The read/write Claim Tag Clear Register is used to read the claim status on
 * debug resources. A read indicates the claim tag status. Writing 1 to a specific
 * bit clears the corresponding claim tag to 0. It is hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtb_tagclear
{
    uint32_t U;
    struct _hw_mtb_tagclear_bitfields
    {
        uint32_t TAGCLEAR : 32;        //!< [31:0]
    } B;
} hw_mtb_tagclear_t;
#endif

/*!
 * @name Constants and macros for entire MTB_TAGCLEAR register
 */
//@{
#define HW_MTB_TAGCLEAR_ADDR     (REGS_MTB_BASE + 0xFA4U)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_TAGCLEAR          (*(__I hw_mtb_tagclear_t *) HW_MTB_TAGCLEAR_ADDR)
#define HW_MTB_TAGCLEAR_RD()     (HW_MTB_TAGCLEAR.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_TAGCLEAR bitfields
 */

/*!
 * @name Register MTB_TAGCLEAR, field TAGCLEAR[31:0] (RO)
 *
 * Hardwired to 0x0000_0000
 */
//@{
#define BP_MTB_TAGCLEAR_TAGCLEAR (0U)      //!< Bit position for MTB_TAGCLEAR_TAGCLEAR.
#define BM_MTB_TAGCLEAR_TAGCLEAR (0xFFFFFFFFU) //!< Bit mask for MTB_TAGCLEAR_TAGCLEAR.
#define BS_MTB_TAGCLEAR_TAGCLEAR (32U)     //!< Bit field size in bits for MTB_TAGCLEAR_TAGCLEAR.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_TAGCLEAR_TAGCLEAR field.
#define BR_MTB_TAGCLEAR_TAGCLEAR (BME_UBFX32(HW_MTB_TAGCLEAR_ADDR, BP_MTB_TAGCLEAR_TAGCLEAR, BS_MTB_TAGCLEAR_TAGCLEAR))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_MTB_LOCKACCESS - Lock Access Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_LOCKACCESS - Lock Access Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * The Lock Access Register enables a write access to component registers. It is
 * hardwired to specific values used during the auto-discovery process by an
 * external debug agent.
 */
typedef union _hw_mtb_lockaccess
{
    uint32_t U;
    struct _hw_mtb_lockaccess_bitfields
    {
        uint32_t LOCKACCESS : 32;      //!< [31:0]
    } B;
} hw_mtb_lockaccess_t;
#endif

/*!
 * @name Constants and macros for entire MTB_LOCKACCESS register
 */
//@{
#define HW_MTB_LOCKACCESS_ADDR   (REGS_MTB_BASE + 0xFB0U)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_LOCKACCESS        (*(__I hw_mtb_lockaccess_t *) HW_MTB_LOCKACCESS_ADDR)
#define HW_MTB_LOCKACCESS_RD()   (HW_MTB_LOCKACCESS.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_LOCKACCESS bitfields
 */

/*!
 * @name Register MTB_LOCKACCESS, field LOCKACCESS[31:0] (RO)
 *
 * Hardwired to 0x0000_0000
 */
//@{
#define BP_MTB_LOCKACCESS_LOCKACCESS (0U)  //!< Bit position for MTB_LOCKACCESS_LOCKACCESS.
#define BM_MTB_LOCKACCESS_LOCKACCESS (0xFFFFFFFFU) //!< Bit mask for MTB_LOCKACCESS_LOCKACCESS.
#define BS_MTB_LOCKACCESS_LOCKACCESS (32U) //!< Bit field size in bits for MTB_LOCKACCESS_LOCKACCESS.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_LOCKACCESS_LOCKACCESS field.
#define BR_MTB_LOCKACCESS_LOCKACCESS (BME_UBFX32(HW_MTB_LOCKACCESS_ADDR, BP_MTB_LOCKACCESS_LOCKACCESS, BS_MTB_LOCKACCESS_LOCKACCESS))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_MTB_LOCKSTAT - Lock Status Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_LOCKSTAT - Lock Status Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * The Lock Status Register indicates the status of the lock control mechanism.
 * This register is used in conjunction with the Lock Access Register. It is
 * hardwired to specific values used during the auto-discovery process by an external
 * debug agent.
 */
typedef union _hw_mtb_lockstat
{
    uint32_t U;
    struct _hw_mtb_lockstat_bitfields
    {
        uint32_t LOCKSTAT : 32;        //!< [31:0]
    } B;
} hw_mtb_lockstat_t;
#endif

/*!
 * @name Constants and macros for entire MTB_LOCKSTAT register
 */
//@{
#define HW_MTB_LOCKSTAT_ADDR     (REGS_MTB_BASE + 0xFB4U)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_LOCKSTAT          (*(__I hw_mtb_lockstat_t *) HW_MTB_LOCKSTAT_ADDR)
#define HW_MTB_LOCKSTAT_RD()     (HW_MTB_LOCKSTAT.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_LOCKSTAT bitfields
 */

/*!
 * @name Register MTB_LOCKSTAT, field LOCKSTAT[31:0] (RO)
 *
 * Hardwired to 0x0000_0000
 */
//@{
#define BP_MTB_LOCKSTAT_LOCKSTAT (0U)      //!< Bit position for MTB_LOCKSTAT_LOCKSTAT.
#define BM_MTB_LOCKSTAT_LOCKSTAT (0xFFFFFFFFU) //!< Bit mask for MTB_LOCKSTAT_LOCKSTAT.
#define BS_MTB_LOCKSTAT_LOCKSTAT (32U)     //!< Bit field size in bits for MTB_LOCKSTAT_LOCKSTAT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_LOCKSTAT_LOCKSTAT field.
#define BR_MTB_LOCKSTAT_LOCKSTAT (BME_UBFX32(HW_MTB_LOCKSTAT_ADDR, BP_MTB_LOCKSTAT_LOCKSTAT, BS_MTB_LOCKSTAT_LOCKSTAT))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_MTB_AUTHSTAT - Authentication Status Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_AUTHSTAT - Authentication Status Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * The Authentication Status Register reports the required security level and
 * current status of the security enable bit pairs. Where functionality changes on
 * a given security level, this change must be reported in this register. It is
 * connected to specific signals used during the auto-discovery process by an
 * external debug agent. MTB_AUTHSTAT[3:2] indicates if nonsecure, noninvasive debug
 * is enabled or disabled, while MTB_AUTHSTAT[1:0] indicates the enabled/disabled
 * state of nonsecure, invasive debug. For both 2-bit fields, 0b10 indicates the
 * functionality is disabled and 0b11 indicates it is enabled.
 */
typedef union _hw_mtb_authstat
{
    uint32_t U;
    struct _hw_mtb_authstat_bitfields
    {
        uint32_t BIT0 : 1;             //!< [0]
        uint32_t BIT1 : 1;             //!< [1]
        uint32_t BIT2 : 1;             //!< [2]
        uint32_t BIT3 : 1;             //!< [3]
        uint32_t RESERVED0 : 28;       //!< [31:4]
    } B;
} hw_mtb_authstat_t;
#endif

/*!
 * @name Constants and macros for entire MTB_AUTHSTAT register
 */
//@{
#define HW_MTB_AUTHSTAT_ADDR     (REGS_MTB_BASE + 0xFB8U)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_AUTHSTAT          (*(__I hw_mtb_authstat_t *) HW_MTB_AUTHSTAT_ADDR)
#define HW_MTB_AUTHSTAT_RD()     (HW_MTB_AUTHSTAT.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_AUTHSTAT bitfields
 */

/*!
 * @name Register MTB_AUTHSTAT, field BIT0[0] (RO)
 *
 * Connected to DBGEN.
 */
//@{
#define BP_MTB_AUTHSTAT_BIT0 (0U)          //!< Bit position for MTB_AUTHSTAT_BIT0.
#define BM_MTB_AUTHSTAT_BIT0 (0x00000001U) //!< Bit mask for MTB_AUTHSTAT_BIT0.
#define BS_MTB_AUTHSTAT_BIT0 (1U)          //!< Bit field size in bits for MTB_AUTHSTAT_BIT0.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_AUTHSTAT_BIT0 field.
#define BR_MTB_AUTHSTAT_BIT0 (BME_UBFX32(HW_MTB_AUTHSTAT_ADDR, BP_MTB_AUTHSTAT_BIT0, BS_MTB_AUTHSTAT_BIT0))
#endif
//@}

/*!
 * @name Register MTB_AUTHSTAT, field BIT1[1] (ROO)
 *
 * Hardwired to 1.
 */
//@{
#define BP_MTB_AUTHSTAT_BIT1 (1U)          //!< Bit position for MTB_AUTHSTAT_BIT1.
#define BM_MTB_AUTHSTAT_BIT1 (0x00000002U) //!< Bit mask for MTB_AUTHSTAT_BIT1.
#define BS_MTB_AUTHSTAT_BIT1 (1U)          //!< Bit field size in bits for MTB_AUTHSTAT_BIT1.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_AUTHSTAT_BIT1 field.
#define BR_MTB_AUTHSTAT_BIT1 (BME_UBFX32(HW_MTB_AUTHSTAT_ADDR, BP_MTB_AUTHSTAT_BIT1, BS_MTB_AUTHSTAT_BIT1))
#endif
//@}

/*!
 * @name Register MTB_AUTHSTAT, field BIT2[2] (RO)
 *
 * Connected to NIDEN or DBGEN signal.
 */
//@{
#define BP_MTB_AUTHSTAT_BIT2 (2U)          //!< Bit position for MTB_AUTHSTAT_BIT2.
#define BM_MTB_AUTHSTAT_BIT2 (0x00000004U) //!< Bit mask for MTB_AUTHSTAT_BIT2.
#define BS_MTB_AUTHSTAT_BIT2 (1U)          //!< Bit field size in bits for MTB_AUTHSTAT_BIT2.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_AUTHSTAT_BIT2 field.
#define BR_MTB_AUTHSTAT_BIT2 (BME_UBFX32(HW_MTB_AUTHSTAT_ADDR, BP_MTB_AUTHSTAT_BIT2, BS_MTB_AUTHSTAT_BIT2))
#endif
//@}

/*!
 * @name Register MTB_AUTHSTAT, field BIT3[3] (ROO)
 *
 * Hardwired to 1.
 */
//@{
#define BP_MTB_AUTHSTAT_BIT3 (3U)          //!< Bit position for MTB_AUTHSTAT_BIT3.
#define BM_MTB_AUTHSTAT_BIT3 (0x00000008U) //!< Bit mask for MTB_AUTHSTAT_BIT3.
#define BS_MTB_AUTHSTAT_BIT3 (1U)          //!< Bit field size in bits for MTB_AUTHSTAT_BIT3.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_AUTHSTAT_BIT3 field.
#define BR_MTB_AUTHSTAT_BIT3 (BME_UBFX32(HW_MTB_AUTHSTAT_ADDR, BP_MTB_AUTHSTAT_BIT3, BS_MTB_AUTHSTAT_BIT3))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_MTB_DEVICEARCH - Device Architecture Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_DEVICEARCH - Device Architecture Register (RO)
 *
 * Reset value: 0x47700A31U
 *
 * This register indicates the device architecture. It is hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtb_devicearch
{
    uint32_t U;
    struct _hw_mtb_devicearch_bitfields
    {
        uint32_t DEVICEARCH : 32;      //!< [31:0]
    } B;
} hw_mtb_devicearch_t;
#endif

/*!
 * @name Constants and macros for entire MTB_DEVICEARCH register
 */
//@{
#define HW_MTB_DEVICEARCH_ADDR   (REGS_MTB_BASE + 0xFBCU)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_DEVICEARCH        (*(__I hw_mtb_devicearch_t *) HW_MTB_DEVICEARCH_ADDR)
#define HW_MTB_DEVICEARCH_RD()   (HW_MTB_DEVICEARCH.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_DEVICEARCH bitfields
 */

/*!
 * @name Register MTB_DEVICEARCH, field DEVICEARCH[31:0] (RO)
 *
 * Hardwired to 0x4770_0A31.
 */
//@{
#define BP_MTB_DEVICEARCH_DEVICEARCH (0U)  //!< Bit position for MTB_DEVICEARCH_DEVICEARCH.
#define BM_MTB_DEVICEARCH_DEVICEARCH (0xFFFFFFFFU) //!< Bit mask for MTB_DEVICEARCH_DEVICEARCH.
#define BS_MTB_DEVICEARCH_DEVICEARCH (32U) //!< Bit field size in bits for MTB_DEVICEARCH_DEVICEARCH.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_DEVICEARCH_DEVICEARCH field.
#define BR_MTB_DEVICEARCH_DEVICEARCH (BME_UBFX32(HW_MTB_DEVICEARCH_ADDR, BP_MTB_DEVICEARCH_DEVICEARCH, BS_MTB_DEVICEARCH_DEVICEARCH))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_MTB_DEVICECFG - Device Configuration Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_DEVICECFG - Device Configuration Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * This register indicates the device configuration. It is hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtb_devicecfg
{
    uint32_t U;
    struct _hw_mtb_devicecfg_bitfields
    {
        uint32_t DEVICECFG : 32;       //!< [31:0]
    } B;
} hw_mtb_devicecfg_t;
#endif

/*!
 * @name Constants and macros for entire MTB_DEVICECFG register
 */
//@{
#define HW_MTB_DEVICECFG_ADDR    (REGS_MTB_BASE + 0xFC8U)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_DEVICECFG         (*(__I hw_mtb_devicecfg_t *) HW_MTB_DEVICECFG_ADDR)
#define HW_MTB_DEVICECFG_RD()    (HW_MTB_DEVICECFG.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_DEVICECFG bitfields
 */

/*!
 * @name Register MTB_DEVICECFG, field DEVICECFG[31:0] (RO)
 *
 * Hardwired to 0x0000_0000.
 */
//@{
#define BP_MTB_DEVICECFG_DEVICECFG (0U)    //!< Bit position for MTB_DEVICECFG_DEVICECFG.
#define BM_MTB_DEVICECFG_DEVICECFG (0xFFFFFFFFU) //!< Bit mask for MTB_DEVICECFG_DEVICECFG.
#define BS_MTB_DEVICECFG_DEVICECFG (32U)   //!< Bit field size in bits for MTB_DEVICECFG_DEVICECFG.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_DEVICECFG_DEVICECFG field.
#define BR_MTB_DEVICECFG_DEVICECFG (BME_UBFX32(HW_MTB_DEVICECFG_ADDR, BP_MTB_DEVICECFG_DEVICECFG, BS_MTB_DEVICECFG_DEVICECFG))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_MTB_DEVICETYPID - Device Type Identifier Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_DEVICETYPID - Device Type Identifier Register (RO)
 *
 * Reset value: 0x00000031U
 *
 * This register indicates the device type ID. It is hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtb_devicetypid
{
    uint32_t U;
    struct _hw_mtb_devicetypid_bitfields
    {
        uint32_t DEVICETYPID : 32;     //!< [31:0]
    } B;
} hw_mtb_devicetypid_t;
#endif

/*!
 * @name Constants and macros for entire MTB_DEVICETYPID register
 */
//@{
#define HW_MTB_DEVICETYPID_ADDR  (REGS_MTB_BASE + 0xFCCU)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_DEVICETYPID       (*(__I hw_mtb_devicetypid_t *) HW_MTB_DEVICETYPID_ADDR)
#define HW_MTB_DEVICETYPID_RD()  (HW_MTB_DEVICETYPID.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_DEVICETYPID bitfields
 */

/*!
 * @name Register MTB_DEVICETYPID, field DEVICETYPID[31:0] (RO)
 *
 * Hardwired to 0x0000_0031.
 */
//@{
#define BP_MTB_DEVICETYPID_DEVICETYPID (0U) //!< Bit position for MTB_DEVICETYPID_DEVICETYPID.
#define BM_MTB_DEVICETYPID_DEVICETYPID (0xFFFFFFFFU) //!< Bit mask for MTB_DEVICETYPID_DEVICETYPID.
#define BS_MTB_DEVICETYPID_DEVICETYPID (32U) //!< Bit field size in bits for MTB_DEVICETYPID_DEVICETYPID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_DEVICETYPID_DEVICETYPID field.
#define BR_MTB_DEVICETYPID_DEVICETYPID (BME_UBFX32(HW_MTB_DEVICETYPID_ADDR, BP_MTB_DEVICETYPID_DEVICETYPID, BS_MTB_DEVICETYPID_DEVICETYPID))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_MTB_PERIPHID4 - Peripheral ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_PERIPHID4 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtb_periphid4
{
    uint32_t U;
    struct _hw_mtb_periphid4_bitfields
    {
        uint32_t PERIPHID : 32;        //!< [31:0]
    } B;
} hw_mtb_periphid4_t;
#endif

/*!
 * @name Constants and macros for entire MTB_PERIPHID4 register
 */
//@{
#define HW_MTB_PERIPHID4_ADDR    (REGS_MTB_BASE + 0xFD0U)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_PERIPHID4         (*(__I hw_mtb_periphid4_t *) HW_MTB_PERIPHID4_ADDR)
#define HW_MTB_PERIPHID4_RD()    (HW_MTB_PERIPHID4.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_PERIPHID4 bitfields
 */

/*!
 * @name Register MTB_PERIPHID4, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to
 * 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000.
 */
//@{
#define BP_MTB_PERIPHID4_PERIPHID (0U)     //!< Bit position for MTB_PERIPHID4_PERIPHID.
#define BM_MTB_PERIPHID4_PERIPHID (0xFFFFFFFFU) //!< Bit mask for MTB_PERIPHID4_PERIPHID.
#define BS_MTB_PERIPHID4_PERIPHID (32U)    //!< Bit field size in bits for MTB_PERIPHID4_PERIPHID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_PERIPHID4_PERIPHID field.
#define BR_MTB_PERIPHID4_PERIPHID (BME_UBFX32(HW_MTB_PERIPHID4_ADDR, BP_MTB_PERIPHID4_PERIPHID, BS_MTB_PERIPHID4_PERIPHID))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_MTB_PERIPHID5 - Peripheral ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_PERIPHID5 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtb_periphid5
{
    uint32_t U;
    struct _hw_mtb_periphid5_bitfields
    {
        uint32_t PERIPHID : 32;        //!< [31:0]
    } B;
} hw_mtb_periphid5_t;
#endif

/*!
 * @name Constants and macros for entire MTB_PERIPHID5 register
 */
//@{
#define HW_MTB_PERIPHID5_ADDR    (REGS_MTB_BASE + 0xFD4U)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_PERIPHID5         (*(__I hw_mtb_periphid5_t *) HW_MTB_PERIPHID5_ADDR)
#define HW_MTB_PERIPHID5_RD()    (HW_MTB_PERIPHID5.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_PERIPHID5 bitfields
 */

/*!
 * @name Register MTB_PERIPHID5, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to
 * 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000.
 */
//@{
#define BP_MTB_PERIPHID5_PERIPHID (0U)     //!< Bit position for MTB_PERIPHID5_PERIPHID.
#define BM_MTB_PERIPHID5_PERIPHID (0xFFFFFFFFU) //!< Bit mask for MTB_PERIPHID5_PERIPHID.
#define BS_MTB_PERIPHID5_PERIPHID (32U)    //!< Bit field size in bits for MTB_PERIPHID5_PERIPHID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_PERIPHID5_PERIPHID field.
#define BR_MTB_PERIPHID5_PERIPHID (BME_UBFX32(HW_MTB_PERIPHID5_ADDR, BP_MTB_PERIPHID5_PERIPHID, BS_MTB_PERIPHID5_PERIPHID))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_MTB_PERIPHID6 - Peripheral ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_PERIPHID6 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtb_periphid6
{
    uint32_t U;
    struct _hw_mtb_periphid6_bitfields
    {
        uint32_t PERIPHID : 32;        //!< [31:0]
    } B;
} hw_mtb_periphid6_t;
#endif

/*!
 * @name Constants and macros for entire MTB_PERIPHID6 register
 */
//@{
#define HW_MTB_PERIPHID6_ADDR    (REGS_MTB_BASE + 0xFD8U)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_PERIPHID6         (*(__I hw_mtb_periphid6_t *) HW_MTB_PERIPHID6_ADDR)
#define HW_MTB_PERIPHID6_RD()    (HW_MTB_PERIPHID6.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_PERIPHID6 bitfields
 */

/*!
 * @name Register MTB_PERIPHID6, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to
 * 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000.
 */
//@{
#define BP_MTB_PERIPHID6_PERIPHID (0U)     //!< Bit position for MTB_PERIPHID6_PERIPHID.
#define BM_MTB_PERIPHID6_PERIPHID (0xFFFFFFFFU) //!< Bit mask for MTB_PERIPHID6_PERIPHID.
#define BS_MTB_PERIPHID6_PERIPHID (32U)    //!< Bit field size in bits for MTB_PERIPHID6_PERIPHID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_PERIPHID6_PERIPHID field.
#define BR_MTB_PERIPHID6_PERIPHID (BME_UBFX32(HW_MTB_PERIPHID6_ADDR, BP_MTB_PERIPHID6_PERIPHID, BS_MTB_PERIPHID6_PERIPHID))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_MTB_PERIPHID7 - Peripheral ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_PERIPHID7 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtb_periphid7
{
    uint32_t U;
    struct _hw_mtb_periphid7_bitfields
    {
        uint32_t PERIPHID : 32;        //!< [31:0]
    } B;
} hw_mtb_periphid7_t;
#endif

/*!
 * @name Constants and macros for entire MTB_PERIPHID7 register
 */
//@{
#define HW_MTB_PERIPHID7_ADDR    (REGS_MTB_BASE + 0xFDCU)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_PERIPHID7         (*(__I hw_mtb_periphid7_t *) HW_MTB_PERIPHID7_ADDR)
#define HW_MTB_PERIPHID7_RD()    (HW_MTB_PERIPHID7.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_PERIPHID7 bitfields
 */

/*!
 * @name Register MTB_PERIPHID7, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to
 * 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000.
 */
//@{
#define BP_MTB_PERIPHID7_PERIPHID (0U)     //!< Bit position for MTB_PERIPHID7_PERIPHID.
#define BM_MTB_PERIPHID7_PERIPHID (0xFFFFFFFFU) //!< Bit mask for MTB_PERIPHID7_PERIPHID.
#define BS_MTB_PERIPHID7_PERIPHID (32U)    //!< Bit field size in bits for MTB_PERIPHID7_PERIPHID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_PERIPHID7_PERIPHID field.
#define BR_MTB_PERIPHID7_PERIPHID (BME_UBFX32(HW_MTB_PERIPHID7_ADDR, BP_MTB_PERIPHID7_PERIPHID, BS_MTB_PERIPHID7_PERIPHID))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_MTB_PERIPHID0 - Peripheral ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_PERIPHID0 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtb_periphid0
{
    uint32_t U;
    struct _hw_mtb_periphid0_bitfields
    {
        uint32_t PERIPHID : 32;        //!< [31:0]
    } B;
} hw_mtb_periphid0_t;
#endif

/*!
 * @name Constants and macros for entire MTB_PERIPHID0 register
 */
//@{
#define HW_MTB_PERIPHID0_ADDR    (REGS_MTB_BASE + 0xFE0U)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_PERIPHID0         (*(__I hw_mtb_periphid0_t *) HW_MTB_PERIPHID0_ADDR)
#define HW_MTB_PERIPHID0_RD()    (HW_MTB_PERIPHID0.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_PERIPHID0 bitfields
 */

/*!
 * @name Register MTB_PERIPHID0, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to
 * 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000.
 */
//@{
#define BP_MTB_PERIPHID0_PERIPHID (0U)     //!< Bit position for MTB_PERIPHID0_PERIPHID.
#define BM_MTB_PERIPHID0_PERIPHID (0xFFFFFFFFU) //!< Bit mask for MTB_PERIPHID0_PERIPHID.
#define BS_MTB_PERIPHID0_PERIPHID (32U)    //!< Bit field size in bits for MTB_PERIPHID0_PERIPHID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_PERIPHID0_PERIPHID field.
#define BR_MTB_PERIPHID0_PERIPHID (BME_UBFX32(HW_MTB_PERIPHID0_ADDR, BP_MTB_PERIPHID0_PERIPHID, BS_MTB_PERIPHID0_PERIPHID))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_MTB_PERIPHID1 - Peripheral ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_PERIPHID1 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtb_periphid1
{
    uint32_t U;
    struct _hw_mtb_periphid1_bitfields
    {
        uint32_t PERIPHID : 32;        //!< [31:0]
    } B;
} hw_mtb_periphid1_t;
#endif

/*!
 * @name Constants and macros for entire MTB_PERIPHID1 register
 */
//@{
#define HW_MTB_PERIPHID1_ADDR    (REGS_MTB_BASE + 0xFE4U)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_PERIPHID1         (*(__I hw_mtb_periphid1_t *) HW_MTB_PERIPHID1_ADDR)
#define HW_MTB_PERIPHID1_RD()    (HW_MTB_PERIPHID1.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_PERIPHID1 bitfields
 */

/*!
 * @name Register MTB_PERIPHID1, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to
 * 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000.
 */
//@{
#define BP_MTB_PERIPHID1_PERIPHID (0U)     //!< Bit position for MTB_PERIPHID1_PERIPHID.
#define BM_MTB_PERIPHID1_PERIPHID (0xFFFFFFFFU) //!< Bit mask for MTB_PERIPHID1_PERIPHID.
#define BS_MTB_PERIPHID1_PERIPHID (32U)    //!< Bit field size in bits for MTB_PERIPHID1_PERIPHID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_PERIPHID1_PERIPHID field.
#define BR_MTB_PERIPHID1_PERIPHID (BME_UBFX32(HW_MTB_PERIPHID1_ADDR, BP_MTB_PERIPHID1_PERIPHID, BS_MTB_PERIPHID1_PERIPHID))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_MTB_PERIPHID2 - Peripheral ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_PERIPHID2 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtb_periphid2
{
    uint32_t U;
    struct _hw_mtb_periphid2_bitfields
    {
        uint32_t PERIPHID : 32;        //!< [31:0]
    } B;
} hw_mtb_periphid2_t;
#endif

/*!
 * @name Constants and macros for entire MTB_PERIPHID2 register
 */
//@{
#define HW_MTB_PERIPHID2_ADDR    (REGS_MTB_BASE + 0xFE8U)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_PERIPHID2         (*(__I hw_mtb_periphid2_t *) HW_MTB_PERIPHID2_ADDR)
#define HW_MTB_PERIPHID2_RD()    (HW_MTB_PERIPHID2.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_PERIPHID2 bitfields
 */

/*!
 * @name Register MTB_PERIPHID2, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to
 * 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000.
 */
//@{
#define BP_MTB_PERIPHID2_PERIPHID (0U)     //!< Bit position for MTB_PERIPHID2_PERIPHID.
#define BM_MTB_PERIPHID2_PERIPHID (0xFFFFFFFFU) //!< Bit mask for MTB_PERIPHID2_PERIPHID.
#define BS_MTB_PERIPHID2_PERIPHID (32U)    //!< Bit field size in bits for MTB_PERIPHID2_PERIPHID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_PERIPHID2_PERIPHID field.
#define BR_MTB_PERIPHID2_PERIPHID (BME_UBFX32(HW_MTB_PERIPHID2_ADDR, BP_MTB_PERIPHID2_PERIPHID, BS_MTB_PERIPHID2_PERIPHID))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_MTB_PERIPHID3 - Peripheral ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_PERIPHID3 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtb_periphid3
{
    uint32_t U;
    struct _hw_mtb_periphid3_bitfields
    {
        uint32_t PERIPHID : 32;        //!< [31:0]
    } B;
} hw_mtb_periphid3_t;
#endif

/*!
 * @name Constants and macros for entire MTB_PERIPHID3 register
 */
//@{
#define HW_MTB_PERIPHID3_ADDR    (REGS_MTB_BASE + 0xFECU)

#ifndef __LANGUAGE_ASM__
#define HW_MTB_PERIPHID3         (*(__I hw_mtb_periphid3_t *) HW_MTB_PERIPHID3_ADDR)
#define HW_MTB_PERIPHID3_RD()    (HW_MTB_PERIPHID3.U)
#endif
//@}

/*
 * Constants & macros for individual MTB_PERIPHID3 bitfields
 */

/*!
 * @name Register MTB_PERIPHID3, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to
 * 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000.
 */
//@{
#define BP_MTB_PERIPHID3_PERIPHID (0U)     //!< Bit position for MTB_PERIPHID3_PERIPHID.
#define BM_MTB_PERIPHID3_PERIPHID (0xFFFFFFFFU) //!< Bit mask for MTB_PERIPHID3_PERIPHID.
#define BS_MTB_PERIPHID3_PERIPHID (32U)    //!< Bit field size in bits for MTB_PERIPHID3_PERIPHID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_PERIPHID3_PERIPHID field.
#define BR_MTB_PERIPHID3_PERIPHID (BME_UBFX32(HW_MTB_PERIPHID3_ADDR, BP_MTB_PERIPHID3_PERIPHID, BS_MTB_PERIPHID3_PERIPHID))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_MTB_COMPIDn - Component ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_MTB_COMPIDn - Component ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the component IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtb_compidn
{
    uint32_t U;
    struct _hw_mtb_compidn_bitfields
    {
        uint32_t COMPID : 32;          //!< [31:0] Component ID
    } B;
} hw_mtb_compidn_t;
#endif

/*!
 * @name Constants and macros for entire MTB_COMPIDn register
 */
//@{
#define HW_MTB_COMPIDn_COUNT (4U)

#define HW_MTB_COMPIDn_ADDR(n)   (REGS_MTB_BASE + 0xFF0U + (0x4U * n))

#ifndef __LANGUAGE_ASM__
#define HW_MTB_COMPIDn(n)        (*(__I hw_mtb_compidn_t *) HW_MTB_COMPIDn_ADDR(n))
#define HW_MTB_COMPIDn_RD(n)     (HW_MTB_COMPIDn(n).U)
#endif
//@}

/*
 * Constants & macros for individual MTB_COMPIDn bitfields
 */

/*!
 * @name Register MTB_COMPIDn, field COMPID[31:0] (RO)
 *
 * Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to
 * 0x0000_0005; ID3 to 0x0000_00B1.
 */
//@{
#define BP_MTB_COMPIDn_COMPID (0U)         //!< Bit position for MTB_COMPIDn_COMPID.
#define BM_MTB_COMPIDn_COMPID (0xFFFFFFFFU) //!< Bit mask for MTB_COMPIDn_COMPID.
#define BS_MTB_COMPIDn_COMPID (32U)        //!< Bit field size in bits for MTB_COMPIDn_COMPID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the MTB_COMPIDn_COMPID field.
#define BR_MTB_COMPIDn_COMPID(n) (BME_UBFX32(HW_MTB_COMPIDn_ADDR(n), BP_MTB_COMPIDn_COMPID, BS_MTB_COMPIDn_COMPID))
#endif
//@}

//-------------------------------------------------------------------------------------------
// hw_mtb_t - module struct
//-------------------------------------------------------------------------------------------
/*!
 * @brief All MTB module registers.
 */
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_mtb
{
    __IO hw_mtb_position_t POSITION;       //!< [0x0] MTB Position Register
    __IO hw_mtb_master_t MASTER;           //!< [0x4] MTB Master Register
    __IO hw_mtb_flow_t FLOW;               //!< [0x8] MTB Flow Register
    __I hw_mtb_base_t BASE;                //!< [0xC] MTB Base Register
    uint8_t _reserved0[3824];
    __I hw_mtb_modectrl_t MODECTRL;        //!< [0xF00] Integration Mode Control Register
    uint8_t _reserved1[156];
    __I hw_mtb_tagset_t TAGSET;            //!< [0xFA0] Claim TAG Set Register
    __I hw_mtb_tagclear_t TAGCLEAR;        //!< [0xFA4] Claim TAG Clear Register
    uint8_t _reserved2[8];
    __I hw_mtb_lockaccess_t LOCKACCESS;    //!< [0xFB0] Lock Access Register
    __I hw_mtb_lockstat_t LOCKSTAT;        //!< [0xFB4] Lock Status Register
    __I hw_mtb_authstat_t AUTHSTAT;        //!< [0xFB8] Authentication Status Register
    __I hw_mtb_devicearch_t DEVICEARCH;    //!< [0xFBC] Device Architecture Register
    uint8_t _reserved3[8];
    __I hw_mtb_devicecfg_t DEVICECFG;      //!< [0xFC8] Device Configuration Register
    __I hw_mtb_devicetypid_t DEVICETYPID;  //!< [0xFCC] Device Type Identifier Register
    __I hw_mtb_periphid4_t PERIPHID4;      //!< [0xFD0] Peripheral ID Register
    __I hw_mtb_periphid5_t PERIPHID5;      //!< [0xFD4] Peripheral ID Register
    __I hw_mtb_periphid6_t PERIPHID6;      //!< [0xFD8] Peripheral ID Register
    __I hw_mtb_periphid7_t PERIPHID7;      //!< [0xFDC] Peripheral ID Register
    __I hw_mtb_periphid0_t PERIPHID0;      //!< [0xFE0] Peripheral ID Register
    __I hw_mtb_periphid1_t PERIPHID1;      //!< [0xFE4] Peripheral ID Register
    __I hw_mtb_periphid2_t PERIPHID2;      //!< [0xFE8] Peripheral ID Register
    __I hw_mtb_periphid3_t PERIPHID3;      //!< [0xFEC] Peripheral ID Register
    __I hw_mtb_compidn_t COMPIDn[4];       //!< [0xFF0] Component ID Register
} hw_mtb_t;
#pragma pack()

//! @brief Macro to access all MTB registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//!     use the '&' operator, like <code>&HW_MTB</code>.
#define HW_MTB         (*(hw_mtb_t *) REGS_MTB_BASE)
#endif

#endif // __HW_MTB_REGISTERS_H__
// v22/130726/0.9
// EOF
